New dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS drams

被引：0

作者：

Wu, Chung-Yu ^{[1
]}

Yu-Yee, Liow ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Hsing Chu, Taiwan

来源：

Proceedings - IEEE International Symposium on Circuits and Systems | 1999年 / 1卷

关键词：

Amplifiers (electronic) - CMOS integrated circuits - Computer simulation - Integrated circuit manufacture - MOSFET devices - Performance - Threshold voltage;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5V without changing the common DRAM process.

引用

共 32 条

[21] Design of A 1.5-V 3-5 GHz CMOS Low-Voltage Transformer-Based Low Noise Amplifier with TR Switch for Computational Intelligence Applications
Lai, Wen Cheng
Su, Yen-Jung
PROCEEDINGS OF 2016 9TH INTERNATIONAL SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE AND DESIGN (ISCID), VOL 2, 2016, : 256 - 259
[22] A new reduced component multi-level inverter with low total standing voltage for renewable and EV application
Karri, Krishna Kumari
Singh, Varsha
Pattnaik, Swapnajit
INTERNATIONAL JOURNAL OF SYSTEM ASSURANCE ENGINEERING AND MANAGEMENT, 2024, 15 (07) : 2978 - 2996
[23] A 1.5V CMOS high-speed 16-bit÷8-bit divider using the quotient-select architecture and true-single-phase bootstrapped dynamic circuit techniques suitable for low-voltage VLSI
Yeh, CC
Lou, JH
Kuo, JB
40TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2, 1998, : 366 - 369
[24] Multi-Level, Low-Voltage Programming of Ferroelectric HfO2/ZrO2 Nanolaminates Integrated in the Back-End-Of-Line
Hamming-Green, Ruben
Ram, Mamidala Saketh
Falcone, Donato Francesco
Noheda, Beatriz
Offrein, Bert Jan
Begon-Lours, Laura
8TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE, EDTM 2024, 2024, : 265 - 267
[25] Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
Shou-biao Tan
Wen-juan Lu
Chun-yu Peng
Zheng-ping Li
You-wu Tao
Jun-ning Chen
Frontiers of Information Technology & Electronic Engineering, 2015, 16 : 700 - 706
[26] Multi-stage dual replica bit-line delay technique for process-variation-robust timing of low voltage SRAM sense amplifier
Tan, Shou-biao
Lu, Wen-juan
Peng, Chun-yu
Li, Zheng-ping
Tao, You-wu
Chen, Jun-ning
FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, 2015, 16 (08) : 700 - 706
[27] Inkjet-Printed Multi-Bit Low-Voltage Fuse-Type Write-Once-Read-Many Memory Cell
Wang, Ruolin
Li, Qiaofeng
Feng, Linrun
Hu, Wei
Liu, Wenjiang
Guo, Xiaojun
IEEE ELECTRON DEVICE LETTERS, 2016, 37 (07) : 862 - 865
[28] An Inrush Current Limit Method for SiC-based Multi-level Grid-connected Converter During Low-Voltage Ride-Through
Li, Haiguo
Gao, Zihan
Ji, Shiqi
Ma, Yiwei
Wang, Fred
2021 THIRTY-SIXTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2021), 2021, : 2044 - 2049
[29] A novel two-port 6T CMOS SRAM cell structure for low-voltage VLSI SRAM with single-bit-line simultaneous read-and-write access (SBLSRWA) capability
Wang, BT
Kuo, JB
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL V: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY, 2000, : 733 - 736
[30] A High-Density Metal-Fuse Technology Featuring a 1.6 V Programmable Low-Voltage Bit Cell With Integrated 1 V Charge Pumps in 22 nm Tri-Gate CMOS
Kulkarni, Sarvesh H.
Chen, Zhanping
Srinivasan, Balaji
Pedersen, Brian
Bhattacharya, Uddalak
Zhang, Kevin
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2016, 51 (04) : 1003 - 1008

← 1 2 3 4 →