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- [1] Wafer scale packaging based on underfill applied at the wafer level for low-cost flip chip processing 49TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE - 1999 PROCEEDINGS, 1999, : 950 - 954
- [2] Wafer scale packaging based on underfill applied at wafer level for low cost flip chip processing 1999 INTERNATIONAL CONFERENCE ON HIGH DENSITY PACKAGING AND MCMS, PROCEEDINGS, 1999, 3830 : 371 - 375
- [3] Coating and dicing of wafer applied underfills for low-cost flip chip processing INTERNATIONAL SYMPOSIUM ON ADVANCED PACKAGING MATERIALS: PROCESSES, PROPERTIES AND INTERFACES, PROCEEDINGS, 2000, : 175 - 179
- [5] Low-cost wafer level packaging process MICROELECTRONIC YIELD, RELIABILITY, AND ADVANCED PACKAGING, 2000, 4229 : 183 - 190
- [6] Backend processing for wafer level chip scale packaging IEEE/CPMT/SEMI(R) 28TH INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 2003, : 187 - 193
- [7] Characterization of flip chip assembly utilizing wafer applied underfill 52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 1380 - 1384
- [8] Low-cost, wafer level underfilling and reliability testing of flip chip devices 54TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, VOLS 1 AND 2, PROCEEDINGS, 2004, : 1492 - 1498
- [9] Flip chip wafer level packaging of a flexible chip scale package (CSP) 1999 INTERNATIONAL SYMPOSIUM ON MICROELECTRONICS, PROCEEDINGS, 1999, 3906 : 555 - 562