Wafer level chip scale packaging - solder joint reliability

被引：0

作者：

Nguyen, L. ^{[1
,2
,3
,4
]}

Kelkar, N. ^{[1
,5
,6
]}

Kao, T. ^{[1
,5
,6
,7
]}

Prabhu, A. ^{[1
,6
]}

Takiar, H. ^{[1
,8
]}

机构：

[1] National Semiconductor Corporation, M/S 19-100, P.O. Box 58090, Santa Clara, CA 95052-8090, United States

[2] Package Technology Group, National Semiconductor

[3] Strat. Plan. and Development Group

[4] MIT, Hertz Foundation

[5] CSP

[6] University of Maryland (CALCE)

[7] Silicon Light Machines, Sunnyvale, CA, United States

[8] Package Technology Group

来源：

International Journal of Microcircuits and Electronic Packaging | / 21卷 / 04期

关键词：

Finite element method - Linear integrated circuits - Mathematical models - Microprocessor chips - Silicon wafers - Soldered joints - Thermal cycling;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

This paper will discuss the solder joint reliability aspects of a new wafer level Chip Scale Package (CSP) form factor. The CSP requires no leadframe or interposer tooling. It is the same size as the die, and was originally developed for low-pin count analog devices for pitches from 0.8 mm down to 0.5 mm. The package has been demonstrated with eutectic solder bumps on 8-lead devices. The form factor can be extended to higher pin counts of up to 144. Underfilling is not required. Various Design of Experiments (DOEs) were performance to determine the best combination of geometry and process parameters that will yield the best thermal cycling performance. The paper will present highlights of the study, in addition to a description of the solder joint performance.

引用

页码：367 / 373