共 50 条
- [1] Design Consideration for SOI gate controlled hybrid transistor operating at low voltage 1998 5TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY PROCEEDINGS, 1998, : 728 - 731
- [2] Design guidelines for SOI gate controlled hybrid transistor operating at low voltage Pan Tao Ti Hsueh Pao, 9 (770-775):
- [3] Back-gate bias effect in the SOI gate controlled hybrid transistor (GCHT) 1997 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 1997, : 157 - 160
- [4] Modeling for the subthreshold current in SOI short channel gate controlled hybrid transistor 1998 IEEE HONG KONG ELECTRON DEVICES MEETING, PROCEEDINGS, 1998, : 118 - 121
- [5] Effect of silicon film thickness on performance of SOI gate controlled hybrid transistor Pan Tao Ti Hsueh Pao/Chinese Journal of Semiconductors, 1999, 20 (08): : 670 - 675
- [9] Threshold voltage model of the SOI 4-gate transistor 2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, : 89 - 90
- [10] Threshold Voltage Sensitivity Reduction of SOI Four Gate Transistor 2012 7TH INTERNATIONAL CONFERENCE ON ELECTRICAL AND COMPUTER ENGINEERING (ICECE), 2012,