Low cost solder flip chip

Since the advent of flip chip packaging technology on the solid logic technology (SLT) of IBM in the early 1960's, a great deal of thought and energy has been invested toward making flip chip cost competitive with wirebonding. While this goal has been occasionally met in the intervening years, the relentless progress of wirebond technology has repeatedly regained the advantage. Thirty-plus years of materials research has created many new processes for the deposition and patterning of the metals used to create solder bumps. Several of these have achieved commercial viability in recent years. This report highlights the most prominent commercial methods, offers some comparative evaluation, and contrasts their merits in a common application environment.