Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability

被引：0
|
作者：
IBM T. J. Watson Research Center, Yorktown Heights, NY 10598, United States [1 ]
不详 [2 ]
机构：
来源：
IEEE J Solid State Circuits | / 8卷 / 1108-1117期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [1] Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability
    Hwang, W
    Gristede, GD
    Sanda, P
    Wang, SY
    Heidel, DF
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (08) : 1108 - 1117
  • [2] Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability
    Hwang, W
    Gristede, GD
    Sanda, PN
    Wang, SY
    Heidel, DF
    IEEE 1998 CUSTOM INTEGRATED CIRCUITS CONFERENCE - PROCEEDINGS, 1998, : 519 - 522
  • [3] A robust self-resetting CMOS 32-bit parallel adder
    Jung, G
    Sundarajan, VA
    Sobelman, GE
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL I, PROCEEDINGS, 2002, : 473 - 476
  • [4] Implementation of a 64-bit Jackson Adder
    McAuley, Tynan
    Koven, William
    Carter, Andrew
    Ning, Paula
    Harris, David Money
    2013 ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, 2013, : 1149 - 1154
  • [5] SOI implementation of a 64-bit adder
    Tran, J.V.
    Mounes-Toussi, F.
    Storino, S.N.
    Stasiak, D.L.
    Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1999, : 573 - 574
  • [6] A 485ps 64-bit parallel adder in 0.18μm CMOS
    Zheng, Dong-Yu
    Sun, Yan
    Li, Shao-Qing
    Fang, Liang
    JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY, 2007, 22 (01) : 25 - 27
  • [7] A 485ps 64-Bit Parallel Adder in 0.18μm CMOS
    Dong-Yu Zheng
    Yan Sun
    Shao-Qing Li
    Liang Fang
    Journal of Computer Science and Technology, 2007, 22 : 25 - 27
  • [8] A 500-MHz, 32-word x 64-bit, eight-port self-resetting CMOS register file
    Hwang, W
    Joshi, RV
    Henkels, WH
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1999, 34 (01) : 56 - 67
  • [9] A 64-bit fast adder with 0.18μm CMOS technology
    Jin, ZP
    Shen, XB
    Bai, YQ
    International Symposium on Communications and Information Technologies 2005, Vols 1 and 2, Proceedings, 2005, : 1167 - 1171
  • [10] A high speed 0.25μm 64-bit CMOS adder design
    Sun, XG
    Mao, ZG
    Lai, FC
    Ye, YZ
    2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, 2001, : 581 - 583
12345