Programmable conductivity of silicon nanowires with side gates by surface charging

被引：0

作者：

Matsukawa, Takashi ^{[1
,2
]}

Kanemaru, Seigo ^{[1
,2
]}

Masahara, Meishoku ^{[1
,2
]}

Nagao, Masayoshi ^{[1
]}

Tanoue, Hisao ^{[1
]}

Itoh, Junji ^{[1
,2
]}

机构：

[1] Nanoelectronics Research Institute, AIST, Tsukuba, Ibaraki 305-8568

[2] CREST, Japan Sci. and Technol. Corp. (JST), Kawaguchi-shi, Saitama 332-0012

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2003年 / 42卷 / 4 B期

关键词：

Quantum wires; Semiconductor device measurements; Semiconductor memories; Silicon-on-insulator technology; Surface charging;

D O I：

10.1143/jjap.42.2422

中图分类号：

学科分类号：

摘要：

Silicon nanowires with programmable conductivity which utilized sensitivity of conductance to surface charging have been investigated in terms of complementary operation of p- and n-type devices. The device fabricated from a silicon-on-insulator (SOI) wafer consists of a nanowire (width ≈ 30 nm) and side gates for control of surface charging onto the nanowire. The wire current clearly exhibited hysteresis by sweeping the side gate voltage at a constant rate. The transistor characteristics obtained using the SOI substrate as a back gate also exhibited programmable threshold voltage by applying a pulse bias to the side gate. Surface potential imaging of the nanowire by means of scanning Maxwell-stress microscopy (SMM) has been carried out for correlating the programmability to surface charging. The SMM images clearly explained the origin of the programmability and the complementary operation of the p- and n-type nanowires.

引用

页码：2422 / 2425

页数：3

共 9 条

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