Xpipes: A network-on-chip architecture for gigascale systems-on-chip

被引：226

作者：

Bertozzi, Davide ^{[1
]}

Benini, Luca ^{[1
]}

机构：

[1] Dipto. Elettron. Info. Sistemistica, University of Bologna, 40136 Bologna, Via Risorgimento

来源：

IEEE Circuits and Systems Magazine | 2004年 / 4卷 / 02期

关键词：

Network instantiation; Networks-on-chip; Pipelining; Reliability; Soft macros; Systems-on-chip;

D O I：

10.1109/MCAS.2004.1330747

中图分类号：

学科分类号：

摘要：

The growing complexity of embedded multi-processor architectures for digital media processing will soon require highly scalable communication infrastructures. Packet switched Networks-on-Chip (NoC) have been proposed to support the trend for Systems-on-Chip integration. In this paper, an advanced NoC architecture, called Xpipes, targeting high performance and reliable communication for on-chip multi-processors is introduced. It consists of a library of soft macros (switches, network interfaces and links) that are design-time composable and tunable so that domain-specific heterogeneous architectures can be instantiated and synthesized. Links can be pipelined with a flexible number of stages to decouple link throughput from its length and to get arbitrary topologies. Moreover, a tool called Xpipes Compiler, which automatically instantiates a customized NoC from the library of soft network components, is used in this paper to test the Xpipes-based synthesis flow for domain-specific communication architectures.

引用

页码：18 / 31

页数：13

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