SEMICONDUCTOR MEASUREMENT TECHNOLOGY: PLANAR TEST STRUCTURES FOR CHARACTERIZING IMPURITIES IN SILICON.

Various test structures such as sheet resistors, p-n junctions, and MOS capacitors and their associated physical models have been developed to characterize dopants and defects in silicon. These structures address various needs within the semiconductor industry for (a) well-designed and miniaturized test structures such as an orthogonal van der Pauw sheet resistor, (b) simple and economical measurements such as the oxide window width of a diffused layer, (c) up-dated values for the resistivity versus dopant density relation, and (d) improved detection methods for identifying defect centers which control the lifetime and leakage currents of devices. Data in graphical form are appended.