Complementary pass-transistor adiabatic logic circuit using three-phase power supply

A new low-power quasi-adiabatic logic, complementary pass-transistor adiabatic logic (CPAL), is presented. The CPAL circuit is driven by a new three-phase power clock, and its non-adiabatic loss on output loads can be effectively reduced by using complementary pass-transistor logic and transmission gates. Furthermore, the minimization of the energy consumption can be obtained by choosing the optimal size of bootstrapped nMOS transistors, thus it has more efficient energy transfer and recovery. A three-phase power supply generator with a small control logic circuit and a single inductor is proposed. An 8-bit adder based on CPAL is designed and verified. With MOSIS 0.25 μm CMOS technology, the CPAL adder consumes only 35% of the dissipated energy of a 2N-2N2P adder and is about 50% of the dissipated energy of a PFAL adder for clock rates ranging from 50 to 200 MHz.