Microprocessor architecture design with ATLAS

被引：0
|
作者：
Zagar, Mario [1 ,2 ,3 ,5 ]
Basch, Danko [1 ,2 ,4 ]
机构：
[1] University of Zagreb
[2] Fac. of Elec. Eng. and Computing, University of Zagreb, Croatia
[3] IEEE, Computer Society
[4] ACM
[5] Fac. of Elec. Eng. and Computing, University of Zagreb, Unska 3, 10000 Zagreb, Croatia
来源：
IEEE Design and Test of Computers | / 14卷 / 03期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：104 / 112
相关论文
共 50 条
  • [21] Functional Atlas of Primary miRNA Maturation by the Microprocessor
    Rice, Greggory M.
    Shivashankar, Varun
    Ma, Eric J.
    Baryza, Jeremy L.
    Nutiu, Razvan
    MOLECULAR CELL, 2020, 80 (05) : 892 - +
  • [22] The alpha 21264 microprocessor architecture
    Kessler, RE
    McLellan, EJ
    Webb, DA
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 90 - 95
  • [23] ALU Meta-module-Based Design Methodology for Microprocessor Architecture Tools
    Wang, Ziming
    Morimoto, Tomoyuki
    Ogita, Tadahiro
    Kawamata, Ryota
    Luo, Jiahui
    Ogawa, Souta
    Tsutsumi, Toshiyuki
    PROCEEDINGS OF NINTH INTERNATIONAL CONGRESS ON INFORMATION AND COMMUNICATION TECHNOLOGY, ICICT 2024, VOL 4, 2024, 1014 : 349 - 369
  • [24] Microprocessor design
    Piguet, C
    LOW POWER DESIGN IN DEEP SUBMICRON ELECTRONICS, 1997, 337 : 513 - 541
  • [25] HIGHLY SERIAL ARCHITECTURE FOR A MICROPROCESSOR
    MONK, J
    JONES, G
    MICROPROCESSORS AND MICROSYSTEMS, 1982, 6 (03) : 117 - 130
  • [26] MICROPROCESSOR DESIGN
    POUNTAIN, D
    BYTE, 1984, 9 (08): : 361 - &
  • [27] The ATLAS EventIndex: architecture, design choices, deployment and first operation experience
    Barberis, D.
    Cardenas Zarate, S. E.
    Cranshaw, J.
    Favareto, A.
    Fernandez Casani, A.
    Gallas, E. J.
    Glasman, C.
    Gonzalez de la Hoz, S.
    Hrivnac, J.
    Malon, D.
    Prokoshin, F.
    Salt Cairols, J.
    Sanchez, J.
    Toebbicke, R.
    Yuan, R.
    21ST INTERNATIONAL CONFERENCE ON COMPUTING IN HIGH ENERGY AND NUCLEAR PHYSICS (CHEP2015), PARTS 1-9, 2015, 664
  • [28] Design and Verification Network Self-adaption Dual-core Microprocessor Architecture
    Hou, Li-Gang
    Wang, Zhong-Chao
    Peng, Xiao-Hong
    Wang, Jin-Hui
    Fan, Fang-Wen
    2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT), 2016, : 365 - 367
  • [29] The ATLAS analysis architecture
    Cranmer, K. S.
    NUCLEAR PHYSICS B-PROCEEDINGS SUPPLEMENTS, 2008, 177 : 126 - 130
  • [30] Design and architecture for low-power/high-speed RISC microprocessor: SuperH
    Maejima, H
    Kainaga, M
    Uchiyama, K
    IEICE TRANSACTIONS ON ELECTRONICS, 1997, E80C (12) : 1539 - 1545
12345