CMOS RADIX-2 SIGNED-DIGIT ADDER BY BINARY CODE REPRESENTATION.

被引：0

作者：

Nakanishi, Tadashi ^{[1
]}

Yamauchi, Hironori ^{[1
]}

Yoshimura, Hiroshi ^{[1
]}

机构：

[1] NTT, Atsugi, Jpn, NTT, Atsugi, Jpn

来源：

Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E | 1986年 / E69卷 / 04期

关键词：

INTEGRATED CIRCUITS - SEMICONDUCTOR DEVICES; MOS;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

A binary code representation whih reduces device count for radix-2 signed-digit arithmetic has been proposed and an adder using this binary code has been designed. Delay time of addition is estimated at 5. 5 ns regardless of digit length using 1. 2 mu m CMOS technology.

引用

页码：261 / 263