Design of a low-voltage BiCMOS four-quadrant analog multiplier

被引：0
|
作者：
Guan, Hui [1 ]
Tang, Yusheng [1 ]
机构：
[1] Shanghai Jiaotong Univ, Shanghai, China
来源：
Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics | 2000年 / 20卷 / 03期
关键词：
Design - Integrated circuits - MOS devices - Signal processing - Simulation;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
A simple low-voltage BiCMOS four-quadrant analog multiplier using BiCMOS linear-region transconductors and pre-input is presented. Its basic configuration and design principle are analyzed in detail. The multiplier is designed in a typical 1.2 μm BiCMOS process and the simulated results are given through SPICE. Simulated results show that for a power supply of ±3 V, the power consumption is less than 2.5 mW, and full-scale linear input range is about ±2 V. Both the total harmonic distortion (THD) and non-linearity error are less than 0.8% with an input range up to ±1.6 V. The simulated -3 dB bandwidth is more than 110 MHz.
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页码：270 / 275
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