DESIGN OF A LOGIC CELL ARRAY BASED TIME-SLOT ASSIGNMENT CIRCUIT.

被引：0

作者：

Dunlop, John ^{[1
]}

Girma, Demessie ^{[1
]}

机构：

[1] Univ of Strathclyde, Glasgow, Scotl, Univ of Strathclyde, Glasgow, Scotl

来源：

Electronic Engineering (London) | 1988年 / 60卷 / 733期

关键词：

DATA STORAGE; SEMICONDUCTOR - Storage Devices - LOGIC DEVICES;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The logic cell array is a device which offers a solution which bridges the gap between PLDs and gate arrays. The LCA implementation of a time slot assignment circuit and its application in a line card are reported. The authors report a 95% utilization of the LCA.

引用

页码：29 / 40