Power and performance comparison of crossbars and buses as on-chip interconnect structures

被引：0
|
作者：
Pennsylvania State Univ, University Park, United States [1 ]
机构：
来源：
Conf Rec Asilomar Conf Signals Syst Comput | / 378-383期
关键词：
Compendex;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
12
引用
收藏
相关论文
共 50 条
  • [21] Predicting the performance and reliability of carbon nanotube bundles for on-chip interconnect
    Nieuwoudt, Arthur
    Mondal, Mosin
    Massoud, Yehia
    PROCEEDINGS OF THE ASP-DAC 2007, 2007, : 708 - +
  • [22] Low-power crosstalk avoidance encoding for on-chip data buses
    Zhang, Qingli
    Wang, Jinxiang
    Ye, Yizheng
    2006 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, 2006, : 1611 - +
  • [23] Skewed repeater bus: A low-power scheme for on-chip buses
    Ghoneima, Maged M.
    Khellah, Muhammad M.
    Tschanz, James
    Ye, Yibin
    Kurd, Nasser
    Barkatullah, Javed S.
    Nimmagadda, Srikanth
    Ismail, Yehea
    De, Vivek K.
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2008, 55 (07) : 1904 - 1910
  • [24] Why transition coding for power minimization of on-chip buses does not work
    Kretzschmar, C
    Nieuwland, AK
    Müller, D
    DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 512 - 517
  • [25] Optimization of On-Chip Interconnect Signaling for Low Energy and High Performance
    Chen, Ge
    Nooshabadi, Saeid
    JOURNAL OF LOW POWER ELECTRONICS, 2012, 8 (01) : 30 - 38
  • [26] EFFICIENT RECONFIGURABLE ON-CHIP BUSES FOR FPGAS
    Koch, Dirk
    Haubelt, Christian
    Teich, Juergen
    PROCEEDINGS OF THE SIXTEENTH IEEE SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, 2008, : 287 - 290
  • [27] A Methodology to Validate the On-Chip Buses of a Microcontroller
    Ashwathnarayan, Meghashyam
    Guddeti, Jayakrishna
    PROCEEDINGS OF 2018 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2018), 2018,
  • [28] Estimation of crosstalk noise for on-chip buses
    Tuuna, S
    Isoaho, J
    INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2003, 2799 : 111 - 120
  • [29] Signal Integrity Verification of Coplanar Structures for Shielded On-Chip Interconnect Lines
    Khan, Zafar Bedar
    Kim, Hyewon
    Eo, Yungseon
    2009 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC 2009), 2009, : 440 - 443
  • [30] Noise Analysis of On-Chip Flexing Crossbars With a Geometric Model
    Erdemir, Sertac
    Oruc, A. Yavuz
    2016 IEEE INTERNATIONAL SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY (EMC), 2016, : 478 - 484
12345