共 50 条
[42]
MULTIPROCESSOR DSP WITH MULTISTAGE SWITCHING NETWORK AND ITS SCHEDULING FOR IMAGE-PROCESSING
[J].
VISUAL COMMUNICATIONS AND IMAGE PROCESSING IV, PTS 1-3,
1989, 1199
:1106-1115
[43]
Synthesis of DSP soft real-time multiprocessor systems-on-silicon
[J].
ICASSP '99: 1999 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, PROCEEDINGS VOLS I-VI,
1999,
:1901-1904
[45]
A delay-optimal static scheduling of DSP applications mapped onto multiprocessor architectures
[J].
PAR ELEC 2006: INTERNATIONAL SYMPOSIUM ON PARALLEL COMPUTING IN ELECTRICAL ENGINEERING, PROCEEDINGS,
2006,
:386-+
[46]
High-performance buffer mapping to exploit DRAM concurrency in multiprocessor DSP systems
[J].
RSP 2009: TWENTIETH IEEE/IFIP INTERNATIONAL SYMPOSIUM ON RAPID SYSTEM PROTOTYPING, PROCEEDINGS: SHORTENING THE PATH FROM SPECIFICATION TO PROTOTYPE,
2009,
:137-+