TIME-REDUNDANT FAULT-LOCATION IN BIT-SLICED ALU'S.

被引：0
|
作者：
Wu, Chwan-Chia [1 ]
机构：
[1] Natl Taiwan Inst of Technology, Taipei, Taiwan, Natl Taiwan Inst of Technology, Taipei, Taiwan
来源：
IEEE Transactions on Computers | 1987年 / C-36卷 / 11期
关键词：
D O I：
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中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A method of fault location in arithmetic and logic units (ALUs) is proposed. When the failures are confined to adjacent bit slices of the ALUs, the RESO (recomputing with shifted operands) based method can isolate the faulty bit slices by specifying a larger set of suspicious faulty bit slices, thus identifying the definitely fault-free bit slices. The method is applicable to both arithmetic and logic operations.
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页码：1387 / 1389
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