共 50 条
- [41] OPTIMUM LSI IMPLEMENTATION FOR A DIGITAL PHASE-LOCKED LOOP IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS, 1978, 25 (04): : 222 - 228
- [45] A Fractional ΔΣ Phase-to-Digital Converter for Digitizing a Phase-Locked Loop 2011 IEEE 54TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS (MWSCAS), 2011,
- [46] DIGITAL CLOCK PHASE-SHIFTER WITHOUT A PHASE-LOCKED LOOP IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS, 1993, 40 (04): : 278 - 283
- [47] The Core Chip Design of Fast Locked All Digital Phase-locked Loop 2019 IEEE 4TH INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS AND MICROSYSTEMS (ICICM 2019), 2019, : 85 - 89
- [48] Extending locked range of digital phase-locked loop by prediction estimation of states Tongxin Xuebao/Journal on Communications, 2008, 29 (09): : 68 - 72
- [49] Markov Model of a Binary Phase Locked Loop. Rozprawy Elektrotechniczne, 1986, 32 (04): : 1069 - 1078
- [50] A high lock-in speed digital phase-locked loop IEEE Transactions on Communications, 1991, 39 (03): : 365 - 368