Value of sequential equivalence checking

被引：0
|
作者：
Kumar, R. [1 ]
Kunz, W. [1 ]
机构：
[1] Verysys Corp
来源：
Electronic Engineering (London) | 1999年 / 71卷 / 869期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
相关论文
共 50 条
  • [21] SEChecker: A Sequential Equivalence Checking Framework Based on Kth Invariants
    Lu, Feng
    Cheng, Kwang-Ting
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2009, 17 (06) : 733 - 746
  • [22] Mining global constraints for improving bounded sequential equivalence checking
    Wu, Weixin
    Hsiao, Michael S.
    43RD DESIGN AUTOMATION CONFERENCE, PROCEEDINGS 2006, 2006, : 743 - 748
  • [23] An efficient sequential equivalence checking framework using Boolean Satisfiability
    Zheng, Feijun
    Weng, Yanling
    Yan, Xiaolang
    ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS, 2007, : 1174 - 1177
  • [24] Equivalence Checking of Bounded Sequential Circuits based on Grobner Basis
    Wang Guanjun
    Zhao Ying
    Tong Minming
    2014 SEVENTH INTERNATIONAL SYMPOSIUM ON COMPUTATIONAL INTELLIGENCE AND DESIGN (ISCID 2014), VOL 2, 2014,
  • [25] Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking
    Rahim, S
    Rouzeyre, B
    Torres, L
    Rampon, J
    EIGHTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS, 2003, : 129 - 134
  • [26] Automatic decomposition for sequential equivalence checking of system level and RTL descriptions
    Vasudevan, Shobha
    Viswanath, Vinod
    Abraham, Jacob A.
    Tu, Jiajin
    FOURTH ACM & IEEE INTERNATIONAL CONFERENCE ON FORMAL METHODS AND MODELS FOR CO-DESIGN, PROCEEDINGS, 2006, : 71 - +
  • [27] Leveraging sequential equivalence checking to enable system-level to RTL flows
    Urard, Pascal
    Maalej, Asma
    Guizzetti, Roberto
    Chawla, Nitin
    Krishnaswamy, Venkatram
    2008 45TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2, 2008, : 816 - 821
  • [28] Mining global constraints with domain knowledge for improving bounded sequential equivalence checking
    Wiu, Weixin
    Hsiao, Michael S.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2008, 27 (01) : 197 - 201
  • [29] Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
    Chen, Yung-Chih
    Ji, Wei-An
    Wang, Chih-Chung
    Huang, Ching-Yi
    Wu, Chia-Cheng
    Lin, Chia-Chun
    Wang, Chun-Yao
    2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2018,
  • [30] Stateless Model Checking Under a Reads-Value-From Equivalence
    Agarwal, Pratyush
    Chatterjee, Krishnendu
    Pathak, Shreya
    Pavlogiannis, Andreas
    Toman, Viktor
    COMPUTER AIDED VERIFICATION (CAV 2021), PT I, 2021, 12759 : 341 - 366
12345