Pass-transistor logic is considered to offer an interesting circuit configuration that may achieve lower power consumption, higher speed, and smaller chip area, than CMOS. This paper describes the pass-transistor logic SPL that places more emphasis on power reduction than on speed improvement, as well as a circuit configuration for SPHL that aims to further reduce power consumption by extending SPL to fit to the system design. The experimental fabrication and evaluation results for an ultra-low power consumption 8-bit microprocessor using those circuits are reported. Operational data and a design method are described that will be important in the design of other pass-transistor logics. The operation energy and the delay in SPL are discussed.