Computer-aided design framework for superconductor circuits

This report describes a Computer-Aided Design (CAD) framework for superconducting digital circuits that will automatically transform a high-level combinational circuit description to a gate-level netlist. The framework involves enhancing the current semiconductor logic synthesis CAD tools developed at UC Berkeley (SIS) for application to superconductor digital circuits. The issues specific to superconducting circuits at the synthesis level include the use of multi-phase ac clocking for combinational logic, latching behavior with resetting time constraints, and dual-rail noninverting logic.