Performance of the PN superscalar processor as estimated by simulation

被引：0

作者：

Arita, Takaya ^{[1
]}

Ito, Hiroaki ^{[1
]}

Sowa, Masahiro ^{[1
]}

机构：

[1] Nagoya Inst of Tech, Nagoya, Japan

来源：

Systems and Computers in Japan | 1992年 / 23卷 / 14期

关键词：

Fine-grain parallel processor - Instruction level parallelism - Multiple instruction-stream execution - Overlapped execution - PN superscalar processor - Token communication time;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

The authors have already proposed the multiple instruction-stream execution system by a function-partitioned superscalar processor, for extracting the fine-grain parallelism. In the proposed system, the processor is divided into a number of heterogeneous processing units and the instruction stream is given separately to the processing units. The processing units communicate the tokens(control pulses) at a higher speed to control the execution of instruction according to the precedence relations among the instructions. This paper considers the prototype model based on three kinds of machine instructions and evaluates the fundamental performances of the proposed execution scheme by simulation. Especially, the following items are examined: (1) load distribution by three kinds of instructions, (2) extracted parallelism and execution time of the program, (3) effect of token communication time and the effect of overlapped execution of token transmission/ reception instructions, and (4) effect of access time of memory unit.

引用

页码：24 / 34