SOI wafer flow process for stencil mask fabrication

被引：0
|
作者：
Butschke, J. [1 ]
Ehrmann, A. [2 ]
Höfflinger, B. [1 ]
Irmscher, M. [1 ]
Käsmaier, R. [2 ]
Letzkus, F. [1 ]
Löschner, H. [3 ]
Mathuni, J. [2 ]
Reuter, C. [1 ]
Schomburg, C. [1 ]
Springer, R. [1 ]
机构：
[1] Inst. fur Mikroelektronik Stuttgart, Allmandring 30a, 70569 Stuttgart, Germany
[2] Siemens AG, Otto-Hahn-Ring 6, 81739 München, Germany
[3] Ionen Mikrofabrikations Syst. GmbH, Schreygasse 3, 1020 Wien, Austria
来源：
Microelectronic Engineering | 1999年 / 46卷 / 01期
关键词：
D O I：
暂无
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：473 / 476
相关论文
共 50 条
  • [1] SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Höfflinger, B
    Irmscher, M
    Käsmaier, R
    Letzkus, F
    Löschner, H
    Mathuni, J
    Reuter, C
    Schomburg, C
    Springer, R
    MICROELECTRONIC ENGINEERING, 1999, 46 (1-4) : 473 - 476
  • [2] PN and SOI wafer flow process for stencil mask fabrication
    Butschke, J
    Ehrmann, A
    Haugeneder, E
    Irmscher, M
    Käsmaier, R
    Kragler, K
    Letzkus, F
    Löschner, H
    Mathuni, J
    Rangelow, IW
    Reuter, C
    Shi, F
    Springer, R
    15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98, 1999, 3665 : 20 - 29
  • [3] Dry etch improvements in the SOI Wafer Flow Process for IPL stencil mask fabrication
    Letzkus, F
    Butschke, J
    Höfflinger, B
    Irmscher, M
    Reuter, C
    Springer, R
    Ehrmann, A
    Mathuni, J
    MICROELECTRONIC ENGINEERING, 2000, 53 (1-4) : 609 - 612
  • [4] p-n junction-based wafer flow process for stencil mask fabrication
    Rangelow, IW
    Shi, F
    Volland, B
    Sossna, E
    Petrashenko, A
    Hudek, P
    Sunyk, R
    Butschke, J
    Letzkus, F
    Springer, R
    Ehrmann, A
    Gross, G
    Kaesmaier, R
    Oelmann, A
    Struck, T
    Unger, G
    Chalupka, A
    Haugeneder, E
    Lammer, G
    Löschner, H
    Tejeda, R
    Lovell, E
    Engelstad, R
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1998, 16 (06): : 3592 - 3598
  • [5] 200-mm EPL stencil mask fabrication by using SOI substrate
    Sugimura, H
    Eguchi, H
    Yoshii, T
    Tamura, A
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 925 - 933
  • [6] Stencil mask ion implantation technology for realistic approach to wafer process
    Tonari, Kazuhiko
    Nishihashi, Tsutomu
    Ishikawa, Michio
    Fujiyama, Junki
    ION IMPLANTATION TECHNOLOGY, 2006, 866 : 401 - +
  • [7] Stencil mask fabrication for cell projection e-Beam lithography with silicon wafer
    Choi, JS
    Yi, SH
    Choi, YY
    Huh, H
    Kim, J
    PHOTOMASK AND X-RAY MASK TECHNOLOGY VI, 1999, 3748 : 486 - 494
  • [8] Influence of SOI wafer stress properties on placement accuracy of stencil masks
    Kamm, FM
    Ehrmann, A
    Schäfer, H
    Butschke, J
    Spinger, R
    Haugeneder, E
    MICROPROCESSES AND NANOTECHNOLOGY 2001, DIGEST OF PAPERS, 2001, : 44 - 44
  • [9] 200-mm EPL stencil mask fabrication and metrology
    Fujita, H
    Takigawa, T
    Ishikawa, M
    Aritsuka, Y
    Yusa, S
    Hoga, M
    Sano, H
    23RD ANNUAL BACUS SYMPOSIUM ON PHOTOMASK TECHNOLOGY, PTS 1 AND 2, 2003, 5256 : 826 - 833
  • [10] LEEPL mask fabrication using SOI substrates
    Yotsui, K
    Suzuki, G
    Tamura, A
    PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY X, 2003, 5130 : 942 - 950
12345