FUNCTIONAL TEST GENERATION FOR DIGITAL CIRCUITS DESCRIBED USING BINARY DECISION DIAGRAMS.

被引：15

作者：

Abadir, Magdy S. ^{[1
]}

Reghbati, Hassan K. ^{[1
]}

机构：

[1] Univ of Southern California, Los, Angeles, CA, USA, Univ of Southern California, Los Angeles, CA, USA

来源：

IEEE Transactions on Computers | 1986年 / C-35卷 / 04期

关键词：

COMPUTER PROGRAMMING - Algorithms - DECISION THEORY AND ANALYSIS - INTEGRATED CIRCUIT TESTING - INTEGRATED CIRCUITS; VLSI; -; Testing;

D O I：

10.1109/TC.1986.1676774

中图分类号：

学科分类号：

摘要：

A test generation methodology is presented for VLSI circuits described at the functional level. A VLSI circuit is modeled as a network of functional modules such as registers adders, RAMs, and MUXs. The functions of the individual modules are described using binary decision diagrams. A functional fault module is developed independent of the implementation details of the circuit. A generalized D algorithm is proposed for generating tests to detect functional as well as gate-level faults. Algorithms which perform fault excitation, implication, D propagation, and line justification on the functional modules are also described.

引用

页码：375 / 379