Logic-based distributed routing for NoCs

被引：45
作者：
Parallel Architectures Group, Technical University of Valencia, Spain [1 ]
机构：
[1] Parallel Architectures Group, Technical University of Valencia
来源：
IEEE Comput. Archit. Lett. | 2008年 / 1卷 / 13-16期
关键词：
Design constraints - Distributed routing - Efficient routing - Heterogeneous cores - Irregular topology - Manufacturing defects - Power-efficient routing - Practical topology;
D O I：
10.1109/L-CA.2007.16
中图分类号：
学科分类号：
摘要：
The design of scalable and reliable interconnection networks for multicore chips (NoCs) introduces new design constraints like power consumption, area, and ultra low latencies. Although 2D meshes are usually proposed for NoCs, heterogeneous cores, manufacturing defects, hard failures, and chip visualization may lead to irregular topologies. In this context, efficient routing becomes a challenge. Although switches can be easily configured to support most routing algorithms and topologies by using routing tables, this solution does not scale in terms of latency and area. We propose a new circuit that removes the need for using routing tables. The new mechanism, referred to as Logic-Based Distributed Routing (LBDR), enables the implementation in NoCs of many routing algorithms for most of the practical topologies we might find in the near future in a multicore chip. From an initial topology and routing algorithm, a set of three bits per switch output port is computed. By using a small logic block, LBDR mimics (demonstrated by evaluation) the behavior of routing algorithms implemented with routing tables. This result is achieved both in regular and irregular topologies. Therefore, LBDR removes the need for using routing tables for distributed routing, thus enabling flexible, fast and power-efficient routing in NoCs.
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页码：13 / 16
页数：3
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