Nonvolatile configuration memory cell for low power field programmable gate array

A new FPGA design using nonvolatile configuration memory (NCM) has been presented. NCM with large On/Off resistance ratio, such as nanoionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Unlike previous FPGAs with nonvolatile programmable wires, we took architecture based approach for designing memory cell, since the cell area of programmable wire cell becomes larger than conventional SRAM-based configuration memory. We designed high-density NCM layout to evaluate the area reduction of configuration memory and verified the area of NCM is about 3.8X smaller than that of SRAM-based configuration memory, while it is 19X larger in the case of the programmable wire than SRAM-based one. It is expected that NCM achieved about over 20 % reduction in total FPGA area. Area reduction of configuration memory also shortens the interconnect length to reduce the interconnect delay. Furthermore, nonvolatility achieves low power consumption with power gating. © 2011 IEEE.