Balanced instruction cache: Reducing conflict misses of direct-mapped caches through balanced subarray accesses

被引：4
作者：
Department of Electrical and Computer Engineering, San Diego State University [1 ]
机构：
[1] Department of Electrical and Computer Engineering, San Diego State University
来源：
IEEE Comput. Archit. Lett. | 2006年 / 1卷 / 2-5期
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D O I：
10.1109/L-CA.2006.5
中图分类号：
学科分类号：
摘要：
It is observed that the limited memory space of direct-mapped caches is not used in balance therefore incurs extra conflict misses. We propose a novel cache organization of a balanced cache, which balances accesses to cache sets at the granularity of cache subarrays. The key technique of the balanced cache is a programmable sitbarray decoder thmugh which the mapping of memory reference addivsses to . cache subarrays can be optimized hence conflict misses of direct-mapped caches can be resolved. The experimental results show that the miss rate of balanced cache is lower than that of the same sized two-way, set-associative caches on average and can be as low as that of the same sized four-way set-associative caches for particular applications. Compared with previous techniques, the balanced cache requires only one cycle to access all cache hits and has the same access time as direct-mapped caches.
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页码：2 / 5
页数：3
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