Cache coherence protocol and implementation for multiprocessors with no-write-allocate caches

被引：0

作者：

Xiu, Si-Wen ^{[1
]}

Huang, Kai ^{[1
]}

Yu, Min ^{[1
]}

Xie, Tian-Yi ^{[1
]}

Ge, Hai-Tong ^{[2
]}

Yan, Xiao-Lang ^{[1
]}

机构：

[1] Institute of VLSI Design, Zhejiang University, Hangzhou

[2] Hangzhou C-SKY Microsystems Co., Ltd, Hangzhou

来源：

Zhejiang Daxue Xuebao (Gongxue Ban)/Journal of Zhejiang University (Engineering Science) | 2015年 / 49卷 / 02期

关键词：

Cache coherence protocol; Multiprocessor; No-write allocate; Write intervention;

D O I：

10.3785/j.issn.1008-973X.2015.02.023

中图分类号：

学科分类号：

摘要：

Against the disadvantages of existing cache coherence protocols for write-back and no-write-allocate caches, a novel write intervention based protocol was proposed and hardware implemented. Taking advantage of this protocol, in some cases the data can be directly written to the peer caches when write miss occurs, Furthermore, both delayed write-back mechanism of dirty data and cache-to-cache copy are supported. And the requested data can be provided as long as there is at least one valid corresponding cache line, avoiding the unnecessary access of the shared memory. Experimental results show that, in comparison to MOESI protocol, the proposed protocol can significantly reduce the accesses of the shared memory, save the dynamic power consumption and power consumption, and improve the performance of the whole system. ©, 2015, Zhejiang University. All right reserved.

引用

页码：351 / 359

页数：8

共 14 条

[1] Zhou X., Yu C., Dash A., Et al., Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors, ACM Transactions on Design Automation of Electronic Systems (TODAES), 13, (2008)
[2] Crawford S.E., Demara R.F., Cache coherence in a multiport memory environment, Proceedings of the First International Conference on Massively Parallel Computing Systems, pp. 632-642, (1994)
[3] Stenstrom P., A survey of cache coherence schemes for multiprocessors, Computer, 23, 6, pp. 12-24, (1990)
[4] Hennessy J.L., Patterson D.A., Computer Architecture: A Quantitative Approach, Fourth Edition, pp. 208-284, (2007)
[5] Leverich J., Arakida H., Solomatnikov A., Et al., Comparing memory systems for chip multiprocessors, ACM SIGARCH Computer Architecture News, 35, 2, pp. 358-368, (2007)
[6] Jang Y.J., Ro W.W., Evaluation of cache coherence protocols on multi-core systems with linear workloads, ISECS International Colloquium on Computing, Communication, Control, and Management, pp. 342-345, (2009)
[7] Yi K., Ro W., Gaudiot J., Importance of coherence protocols with network applications on multi-Core processors, IEEE Transactions on Computers, 62, 1, pp. 6-15, (2013)
[8] Li J.M., Liu W.J., Jiao P., A new kind of cache coherence protocol with sc-cache for multiprocessor, 2010 2nd International Workshop on Intelligent Systems and Applications (ISA), pp. 1-5, (2010)
[9] Kaxiras S., Ros A., Efficient, snoopless, system-on-chip coherence, SOC Conference (SOCC), pp. 230-235, (2012)
[10] Hackenberg D., Molka D., Nagel W.E., Comparing cache architectures and coherency protocols on x86-64 multicore SMP systems, Proceedings of the 42nd Annual IEEE/ACM International Symposium on microarchitecture, pp. 413-422, (2009)

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