An Implementation of a World Grid Square Codes Generator on a RISC-V Processor

被引：0
|
作者：
Watanabe, Rei [1 ]
Tada, Jubee [1 ]
Sato, Keiichi [2 ]
机构：
[1] Graduate School of Science And Engineering, Yamagata University, Yonezawa, Japan
[2] Yamagata College of Industry And Technology, Department of Information Systems, Yamagata, Japan
来源：
Proceedings - 2021 9th International Symposium on Computing and Networking Workshops, CANDARW 2021 | 2021年
关键词：
Compilation and indexing terms; Copyright 2025 Elsevier Inc;
D O I：
暂无
中图分类号：
学科分类号：
摘要：
Signal encoding - Reduced instruction set computing - Field programmable gate arrays (FPGA)
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页码：309 / 312
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