A Low-Power 1-V Supply Dynamic Comparator

被引：0

作者：

Chevella S. ^{[1
]}

O'Hare D. ^{[1
]}

O'Connell I. ^{[1
]}

机构：

[1] Precision Circuits, Microelectronic Circuits Centre Ireland, Tyndall National Institute, Cork

来源：

Chevella, Subhash (subhash.chevella@mcci.ie); Chevella, Subhash (subhash.chevella@mcci.ie) | 1600年 / Institute of Electrical and Electronics Engineers Inc.卷 / 03期

关键词：

Analog-to-digital converter (ADC); comparator; double-tail latch-type comparator; latch; low-noise; low-power; SAR; StrongArm;

D O I：

10.1109/lssc.2020.3009437

中图分类号：

学科分类号：

摘要：

This letter presents a low-power dynamic comparator for ultralow power applications. The prototype is designed in a 65-nm CMOS process with a supply voltage of 1 V and is compared against the widely used double tail latch comparator in terms of power consumption and input referred rms noise. The addition of cross-coupled devices to the input differential pair prevents the comparator internal nodes from fully discharging to ground in contrast to the conventional architecture. This reduces the power consumption while achieving similar noise levels. Measurements demonstrate that the proposed comparator achieves an input referred rms noise voltage of 220 μV against 210 μV for the conventional comparator with a 30% reduction in power. The proposed circuit consumes 0.19-pJ energy per comparison.. © 2018 IEEE.

引用

页码：154 / 157

页数：3

共 7 条

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