共 50 条
- [1] FPGA implementation of the JPEG2000 binary arithmetic (MQ) decoder Journal of Real-Time Image Processing, 2013, 8 : 411 - 419
- [2] Reduced latency arithmetic decoder for JPEG2000 block decoding 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2076 - 2079
- [4] Implementation of JPEG2000 arithmetic decoder on a dynamically reconfigurable ATMEL FPGA VLSI 2004: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS, 2004, : 237 - 238
- [5] Implementation of JPEG2000 arithmetic decoder using dynamic reconfiguration of FPGA ICIP: 2004 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1- 5, 2004, : 2841 - 2844
- [6] Design and Implementation of JPEG2000 Arithmetic Decoder based on Handel-C PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON ANTI-COUNTERFEITING, SECURITY, AND IDENTIFICATION IN COMMUNICATION, 2009, : 505 - 508
- [8] A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000 Journal of Signal Processing Systems, 2015, 81 : 227 - 247
- [9] A High-Throughput VLSI Architecture Design of Arithmetic Encoder in JPEG2000 JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2015, 81 (02): : 227 - 247
- [10] VLSI architecture of DWT for JPEG2000 Tien Tzu Hsueh Pao/Acta Electronica Sinica, 2002, 30 (11): : 1609 - 1612