共 10 条
- [1] Choi W.Y., Park B.G., Lee J.D., Liu T.K., Tunneling field effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec, IEEE Electron Device Lett., 28, pp. 743-745, (2007)
- [2] Jacobson Z.A., Kim S.H., Matheu P., Liu T.-J.K., Source design optimization for the planar ge-source n-channel TFET, Solid-State Electronics, (2011)
- [3] Vandenberghe W.G., Verhuist A.S., Groeseneken G., Soree B., Magnus W., Analytical model for point and line tunneling in a tunnel field-effect transistor, Proceedings of International Conference on Simulation of Semiconductor Processes and Devices, pp. 137-140, (2008)
- [4] Kao K.-H., Verhuist A.S., Vandenberghe W.G., Modeling the impact of junction angles in tunnel field-effect transistors, Solid-State Electronics, 69, pp. 31-37, (2012)
- [5] Boucart K., Ionescu A.M., Double gate tunnel FET with ultrathin silicon body and high-k gate dielectric, ESSDERC, pp. 383-386, (2006)
- [6] Ionescu A.M., Riel H., Tunnel field-effect transistors as energy efficient electronic switches, Nature, 497, pp. 329-337, (2011)
- [7] Nikam V., Bhuwalka K.K., Kottantharayil A., Optimization of n- and p-channel heterojunction tunnel FETs for sub 22 nm gate lengths, Proc. Device Res. Conf., pp. 77-78, (2008)
- [8] Boucart K., Ionescu A.M., Double-gate tunnel FET with high-K gate dielectric, IEEE Trans. Electron Devices, 54, 7, pp. 1725-1733, (2007)
- [9] Pal A., Sachid A.B., Gossner H., Ramgopal Rao V., Insights into the design and optimization of tunnel-FET devices and circuits, IEEE Trans. Electron Devices, 58, 4, pp. 1045-1053, (2011)
- [10] Wang P.-F., Nirschl T., Schmitt-Landsiedel D., Hansen W., Simulation of esaki tunneling FET, Solid-State Electronics, 47, pp. 1187-1192, (2003)