共 16 条
[1]
Singh H., Gill S.S., Approaches to channel equalization, Advanced Computing and Communication Technologies (ACCT), pp. 172-175, (2012)
[2]
Song S.-Q., Stojanovic V., A 6.25 Gb/s voltage-time conversion based fractionally spaced linear receive equalizer for mesochronous high-speed links, Solid-State Circuits, 46, 5, pp. 1183-1197, (2011)
[3]
Lee H., Chang K.Y.K., Chun J.H., Et al., A 16 Gb/s link, 64 GB/s bidirectional asymmetric memory interface, Solid-State Circuits, 44, 4, pp. 1235-1247, (2009)
[4]
Balamurugan G., Casper B., Jaussi J.E., Et al., Modeling and analysis of high-speed I/O links, Advanced Packaging, 32, 2, pp. 237-247, (2009)
[5]
Analui B., Buckwalter J.F., Hajimiri A., Data-dependent jitter in serial communications, Microwave Theory and Techniques, 53, 11, pp. 3388-3397, (2005)
[6]
Liu C., Caroselli J., Comparison of signaling and equalization schemes in high speed SerDes (10-25 Gb/s), DesignCon., (2007)
[7]
Caroselli J., Liu C., An analytic system model for high speed interconnects and its application to the specification of signaling and equalization architectures for 10Gbps backplane communication, DesignCon., (2006)
[8]
Yao W., Shi Y.-Y., He L., Et al., Worst-case estimation for data-dependent timing jitter and amplitude noise in high-speed differential link, Very Large Scale Integration (VLSI) Systems, 20, 1, pp. 89-97, (2012)
[9]
Zhong H., Zheng L.-H., Jin G.-P., Bit-rate maximization frequency-domain equalization algorithm for FMT systems, Journal of Electronics and Information Technology, 32, 6, pp. 1429-1434, (2010)
[10]
Bajpai A., Lakshmanan M.K., Nikookar H., Channel equalization in wavelet packet modulation by minimization of peak distortion, Personal Indoor and Mobile Radio Communications (PIMRC), pp. 152-156, (2011)