Stacking chips in 3D

被引：0

作者：

机构：

来源：

IEEE Des Test Comput | 2009年 / 5卷 / 02期

关键词：

D O I：

10.1109/MDT.2009.122

中图分类号：

学科分类号：

摘要：

3D IC solutions have been developed for several different reasons: to reduce the system form factor for portable platforms; to increase system performance by alleviating the interconnect-delay bottleneck; and to manage overall system cost by stacking heterogeneous chips, rather than integrate diverse system components into a single chip through 2D scaling. However, although some 3D IC markets are emerging, and most technical issues of 3D integration are almost solved, several thermal and production-test challenges remain as obstacles. This special issue of IEEE Design & Test takes a look a those issues. © 2009 IEEE.

引用