Hierarchical high speed testing and verification of chip-multiprocessors

被引：0

作者：

Guo, Song-Liu ^{[1
,2
]}

Wang, Dong-Sheng ^{[1
]}

Yao, Wen-Bin ^{[2
]}

机构：

[1] Microprocessor and SoC Technology R and D Center, Tsinghua University, Beijing 100084, China

[2] Centre of High Dependability Computing Technology, Harbin Engineering University, Harbin 150001, China

来源：

Harbin Gongcheng Daxue Xuebao/Journal of Harbin Engineering University | 2007年 / 28卷 / 05期

关键词：

Architecture - Computer simulation - Computer software - Parallel processing systems - Program processors - Reliability - Scalability - Testing - Verification;

D O I：

暂无

中图分类号：

学科分类号：

摘要：

CMP (Chip-Multi-Processor) is a high performance architecture with low power consumption. As the scale of the chip's logic is huge, and all parts of the memory system must be reliable, verification and testing of a CMP system is complicated and time consuming. The speed of testing using traditional methods of verification will be very slow. Breaking the testing process into discrete segments can reduce complexity and the computing workload, saving significant time. (Constrained random program generation, CRTPG) testing also reduces the work of the tester and finds bugs rapidly. Parallel testing and verification allows completion of testing in a shorter time with low power consumption and good scalability. Integrating all these methods in CMP testing can effectively share the workload of testing through effective parallelism, find bugs and mistakes quickly, reduce the time needed for testing and verification work and improve the coverage ratio of testing and thus, the reliability of the whole system.

引用

页码：566 / 570