Machine Learning for Microarchitecture Power Modeling and Design Space Exploration: A Survey

被引:0
作者
Zhai, Jianwang [1 ]
Ling, Zichao [2 ]
Bai, Chen [3 ]
Zhao, Kang [1 ]
Yu, Bei [3 ]
机构
[1] School of Integrated Circuits, Beijing University of Posts and Telecommunications, Beijing
[2] School of Computer Science, Beijing University of Posts and Telecommunications, Beijing
[3] Department of Computer Science and Engineering, The Chinese University of Hong Kong
来源
Jisuanji Yanjiu yu Fazhan/Computer Research and Development | 2024年 / 61卷 / 06期
关键词
design space exploration; machine learning; microarchitecture design; power modeling; processor design automation;
D O I
10.7544/issn1000-1239.202440074
中图分类号
学科分类号
摘要
Microarchitecture design is a key stage of processor development. It is at the upper level of the entire design flow and directly affects core metrics such as performance, power consumption, and cost. Over the past few decades, new microarchitecture solutions, coupled with advances in semiconductor manufacturing, have enabled newer generations of processors to achieve higher performance, lower power consumption and cost. However, as chip design enters the post-Moore era, the dividends from the evolution of semiconductor technology are increasingly limited, and power consumption has become a major challenge for energy-efficient processor design. Meanwhile, modern processors are becoming more complex in architecture and the design space is larger, requiring designers to make accurate design metrics tradeoffs to achieve the most desirable microarchitecture design. Moreover, the existing stage-by-stage decomposition of the development and validation flow is extremely lengthy and time-consuming, and it is difficult to achieve global energy efficiency optimization. Therefore, how to perform accurate and efficient power estimation and design space exploration at the microarchitecture design stage becomes a key issue. To tackle these challenges, machine learning has been introduced into the microarchitecture design process, providing efficient and accurate solutions for microarchitecture modeling and optimization. We firstly introduce the main design flow of processors, microarchitecture design and its major challenges, then amplify machine learning-assisted integrated circuit design, which focuses on research advances in the use of machine learning techniques to assist microarchitecture power modeling and design space exploration, and finally conclude with a summary and outlook. © 2024 Science Press. All rights reserved.
引用
收藏
页码:1351 / 1369
页数:18
相关论文
共 92 条
  • [1] Several policies to promote the high-quality development of integrated circuit industry and software industry in the new era
  • [2] Yunqi Chen, Yimao Cai, Wang Yu, Et al., Integrated circuit technology: Future development and key issues–review of the 347th Shuangqing Forum (Youth)[J], SCIENTIA SINICA Informationis, 54, 1, (2024)
  • [3] Chengxiang Xiang, Yongan Yang, Penner R M., Cheating the diffraction limit: Electrodeposited nanowires patterned by photolithography[J], Chemical Communications, 8, pp. 859-873, (2009)
  • [4] Chaudhry A, Kumar M J., Controlling short-channel effects in deep-submicron SOI MOSFETs for improved reliability: A review[J], IEEE Transactions on Device and Materials Reliability, 4, 1, (2004)
  • [5] Thimbleby H., Modes, WYSIWYG and the von Neumann bottleneck, Proc of IEE Colloquium on Formal Methods and Human-Computer Interaction: II, (1988)
  • [6] Zhou Zhihua, Machine Learning, (2021)
  • [7] Yun Liang, Cheng Zhuo, Yongfu Li, The shift-left design paradigm of EDA: Progress and challenges[J], SCIENTIA SINICA Informationis, 54, 1, pp. 121-129, (2024)
  • [8] Yungang Bao, Yisong Chang, Yinhe Han, Et al., Agile design of processor chips: Issues and challenges[J], Journal of Computer Research and Development, 58, 6, pp. 1131-1145, (2021)
  • [9] Scheffer L, Lavagno L., EDA for IC System Design, Verification, and Testing, (2018)
  • [10] Wu C M, Shieh M D, Wu C H, Et al., VLSI architectural design tradeoffs for sliding-window log-MAP decoders[J], IEEE Transactions on Very Large Scale Integration Systems, 13, 4, (2005)