Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration

被引:0
|
作者
Taghipour, Pouya [1 ]
Granger, Eric [2 ]
Blaquiere, Yves [1 ]
机构
[1] Ecole Technol Super ETS, Dept Elect Engn, LaCIME, Montreal, PQ H3C 1K3, Canada
[2] Ecole Technol Super ETS, Dept Syst Engn, LIVIA, ILLS, Montreal, PQ H3C 1K3, Canada
来源
IEEE ACCESS | 2024年 / 12卷
基金
加拿大自然科学与工程研究理事会;
关键词
Accuracy; Predictive models; Analytical models; Costs; Codes; Training; Graph neural networks; Standards; Optimization; Logic; Electronic design automation (EDA); high-level synthesis (HLS); design space exploration (DSE); machine learning (ML); graph neural networks (GNN); field-programmable gate array (FPGA);
D O I
10.1109/ACCESS.2024.3509606
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
Optimizing hardware accelerators in high-level synthesis (HLS) relies on design space exploration (DSE), which involves experimenting with different pragma options and trading off hardware cost and performance metrics (HCPMs) to identify Pareto-optimal solutions. The exponential growth of the design space, poor quality-of-results (QoR) estimation by HLS tools, and lengthy post-implementation runtime have made the HLS DSE process highly challenging and time-consuming. Automating this process could reduce time-to-market and associated development costs. Learning-based methods, particularly graph neural networks (GNNs), have shown considerable potential in addressing HLS QoR/DSE problems by modeling the mapping function from control data flow graphs (CDFGs) of HLS designs to their logic, enabling early estimation of QoR during the compilation phase of the hardware design flow. However, there is still a gap in terms of their prediction accuracy. Indeed, modeling HLS-related problems using GNNs that efficiently capture the complex patterns arising from applied pragmas and low-level characteristics of HLS specifications is challenging. This paper introduces a novel hybrid graph representation and learning framework under a multi-task setting, featuring two distinct types of CDFGs derived from two different sources. Furthermore, various models are proposed to fuse features and knowledge in joint, sequential, and parallel learning architectures, aiming to improve the overall accuracy and generalization in predicting QoR and approximating the Pareto frontier (PF). Experimental results show that our framework can attain a higher level of performance than the state-of-the-art baseline models over unseen designs, with an average relative improvement of 47.4 % and 16.0 % for resource utilization and performance metrics, respectively. Additionally, considering various HLS designs with different design space sizes, a 26.8 % enhancement in DSE PF approximation is observed.
引用
收藏
页码:189574 / 189589
页数:16
相关论文
共 50 条
  • [21] GNNHLS: Evaluating Graph Neural Network Inference via High-Level Synthesis
    Zhao, Chenfeng
    Dong, Zehao
    Chen, Yixin
    Zhang, Xuan
    Chamberlain, Roger D.
    2023 IEEE 41ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, ICCD, 2023, : 574 - 577
  • [22] Machine Learning Based Design Space Exploration for Hybrid Main-Memory Design
    Sen, Satyabrata
    Imam, Neena
    MEMSYS 2019: PROCEEDINGS OF THE INTERNATIONAL SYMPOSIUM ON MEMORY SYSTEMS, 2019, : 480 - 489
  • [23] Interleaving Methods for Hybrid System-level MPSoC Design Space Exploration
    Piscitelli, Roberta
    Pimentel, Andy D.
    2012 INTERNATIONAL CONFERENCE ON EMBEDDED COMPUTER SYSTEMS (SAMOS): ARCHITECTURES, MODELING AND SIMULATION, 2012, : 7 - 14
  • [24] Graph explicit pooling for graph-level representation learning
    Liu, Chuang
    Yu, Wenhang
    Gao, Kuang
    Ma, Xueqi
    Zhan, Yibing
    Wu, Jia
    Hu, Wenbin
    Du, Bo
    NEURAL NETWORKS, 2025, 181
  • [25] Graph Representation Learning In A Contrastive Framework For Community Detection
    Balouchi, Mehdi
    Ahmadi, Ali
    2021 26TH INTERNATIONAL COMPUTER CONFERENCE, COMPUTER SOCIETY OF IRAN (CSICC), 2021,
  • [26] A Meta-Framework for Design Space Exploration
    Saxena, Tripti
    Karsai, Gabor
    18TH IEEE INTERNATIONAL CONFERENCE AND WORKSHOPS ON ENGINEERING OF COMPUTER BASED SYSTEMS (ECBS 2011), 2011, : 71 - 80
  • [27] Fast Resource and Timing Aware Design Optimisation for High-Level Synthesis
    Perina, Andre B.
    Silitonga, Arthur
    Becker, Jurgen
    Bonato, Vanderlei
    IEEE TRANSACTIONS ON COMPUTERS, 2021, 70 (12) : 2070 - 2082
  • [28] Malware Detection by Control-Flow Graph Level Representation Learning With Graph Isomorphism Network
    Gao, Yun
    Hasegawa, Hirokazu
    Yamaguchi, Yukiko
    Shimada, Hajime
    IEEE ACCESS, 2022, 10 : 111830 - 111841
  • [29] A hybrid deep-learning-metaheuristic framework for bi-level network design problems
    Madadi, Bahman
    Correia, Goncalo Homem de Almeida
    EXPERT SYSTEMS WITH APPLICATIONS, 2024, 243
  • [30] An Exploration Framework for Efficient High-Level Synthesis of Support Vector Machines: Case Study on ECG Arrhythmia Detection for Xilinx Zynq SoC
    Tsoutsouras, Vasileios
    Koliogeorgi, Konstantina
    Xydis, Sotirios
    Soudris, Dimitrios
    JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 2017, 88 (02): : 127 - 147