FPGA implementation of IIR elliptic filters for de-noising ECG signal

De-noising of ECG signal is very much necessary to monitor the heart health and to diagnose disease. This paper presents a real time de-noising system that efficiently wiped out the noises from corrupted ECG signal and improves its SNR which enhances the interpretation of features present in ECG signal. This proposed system is designed with three Infinite Impulse Response (IIR) elliptic filters in cascaded direct form II structure and is implemented on the FPGA platform. Total 376 ECG samples are taken from the open access public database physiobank. All the architectural level FPGA designs have been developed in Xilinx System Generator (XSG) and implemented on Xilinx Zynq 7000 board. Our design utilized only 3.87 % of the total available resource and consumed 0.321 watt on-chip power. Worst Negative Slack (WNS) for the critical path is 2.101 ns. The positive value of WNS signifies our hardware design implementation run successfully by meeting the required time constraint. To judge the performance of the proposed design, the measurement matrices SNR Improvement, RMSE, PRD, SSNR and SINAD are calculated and achieved 81.11% , 88.89% and 85.41% accuracy for ECG recordings of ECG-ID, MIT-BIH Normal Sinus Rhythm and MIT-BIH Arrhythmia database respectively. The novelty of this proposed denoising system is its robustness, which work satisfactorily for Baseline Wander (BW), Electrode Motion (EM), Power Line Interference (PLI), Muscle or Electromyography (EMG) and as well as Additive White Gaussian Noise (AWGN).