Empirical quantitative modeling of threshold voltage of sub-50-nm double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistor

被引：0

作者：

Tamara, Yuki ^{[1
]}

Omura, Yasuhisa ^{[1
,2
]}

机构：

[1] Graduate School of Engineering, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

[2] OEDIST, Kansai University, 3-3-35 Yamate-cho, Suita, Osaka 564-8680, Japan

来源：

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers | 2006年 / 45卷 / 4 B期

关键词：

We simulated the threhold voltage characteristics of an ultrathin double-gate (DG) silicon-on-insulator metal-oxide-semiconductor field-effect transistor (SOI MOSFET) using the hydrodynamic transport model. It has been shown that threshold voltage increases as SOI layer thickness is reduced in many cases; which is not due to a distinct quantum effect. This stems from an increase in surface potential at the threshold; this increase in surface potential is a physically inevitable result because a reduction in SOI layer thickness decreases inversion layer carrier density per unit area. We proposed models of threshold voltage and surface potential at the threshold; and their availabilities were confirmed by comparing what with the detailed simulation results. We also addressed the short-channel effect on surface potential and proposed a model of drain-induced barrier lowering. © 2006 The Japan Society of Applied Physics;

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摘要：

Journal article (JA)

引用

页码：3074 / 3078

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