Vina-FPGA-Cluster: Multi-FPGA Based Molecular Docking Tool With High-Accuracy and Multi-Level Parallelism

被引:0
作者
Ling, Ming [1 ]
Feng, Zhihao [1 ]
Chen, Ruiqi [1 ]
Shao, Yi [1 ]
Tang, Shidi [1 ]
Zhu, Yanxiang [2 ]
机构
[1] Southeast Univ, Natl ASIC Syst Engn Technol Res Ctr, Nanjing 210096, Peoples R China
[2] Nanjing Renmian Integrated Circuit Co Ltd, VeriMake Innovat Lab, Nanjing 210088, Peoples R China
基金
中国国家自然科学基金;
关键词
Field programmable gate arrays; Parallel processing; Quantization (signal); Proteins; Hardware acceleration; Graphics processing units; Computer architecture; AutoDock Vina (Vina); hardware accelerator; field-programmable gate array (FPGA) cluster; software/hardware (SW/HW) co-design; AUTODOCK VINA; AUTOMATED DOCKING;
D O I
10.1109/TBCAS.2024.3388323
中图分类号
R318 [生物医学工程];
学科分类号
0831 ;
摘要
AutoDock Vina (Vina) stands out among numerous molecular docking tools due to its precision and comparatively high speed, playing a key role in the drug discovery process. Hardware acceleration of Vina on FPGA platforms offers a high energy-efficiency approach to speed up the docking process. However, previous FPGA-based Vina accelerators exhibit several shortcomings: 1) Simple uniform quantization results in inevitable accuracy drop; 2) Due to Vina's complex computing process, the evaluation and optimization phase for hardware design becomes extended; 3) The iterative computations in Vina constrain the potential for further parallelization. 4) The system's scalability is limited by its unwieldy architecture. To address the above challenges, we propose Vina-FPGA-cluster, a multi-FPGA-based molecular docking tool enabling high-accuracy and multi-level parallel Vina acceleration. Standing upon the shoulders of Vina-FPGA, we first adapt hybrid fixed-point quantization to minimize accuracy loss. We then propose a SystemC-based model, accelerating the hardware accelerator architecture design evaluation. Next, we propose a novel bidirectional AG module for data-level parallelism. Finally, we optimize the system architecture for scalable deployment on multiple Xilinx ZCU104 boards, achieving task-level parallelism. Vina-FPGA-cluster is tested on three representative molecular docking datasets. The experiment results indicate that in the context of RMSD (for successful docking outcomes with metrics below 2 & Aring;), Vina-FPGA-cluster shows a mere 0.2% lose. Relative to CPU and Vina-FPGA, Vina-FPGA-cluster achieves 27.33x and 7.26x speedup, respectively. Notably, Vina-FPGA-cluster is able to deliver the 1.38x speedup as GPU implementation (Vina-GPU), with just the 28.99% power consumption.
引用
收藏
页码:1321 / 1337
页数:17
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