0.8 V low power high-speed 1:2 frequency divider

被引：0

作者：

Su Y. ^{[1
]}

Feng J. ^{[1
]}

Shi H. ^{[1
]}

机构：

[1] Institute of RF- and OE-ICs, Southeast University

来源：

Dongnan Daxue Xuebao (Ziran Kexue Ban)/Journal of Southeast University (Natural Science Edition) | 2010年 / 40卷 / 06期

关键词：

Frequency divider; Low voltage; Single-end dynamic loading latch;

D O I：

10.3969/j.issn.1001-0505.2010.06.005

中图分类号：

学科分类号：

摘要：

By using the United Microelectronics Corporation(UMC) 0.13 μm standard complementary metal oxide semiconductor(CMOS) process, a 1:2 frequency divider, which can work on the maximum operation frequency up to 17 GHz, is designed. The circuits are composed of a frequency divider cell and input/output(I/O) buffers. To design a frequency divider working under a low supply voltage, the structure characteristics of different high speed latches are analyzed and a single-end dynamic loading latch is employed as the basic cell. The direct current (DC) analysis is carried out on the single-end dynamic loading latch. Lowering the supply voltage exhibits a more obvious effect on the sensing mode than on the latching mode. The test results show that the lowest supply voltage on which the divider can work is 0.8 V. The frequency range is 3 to 17 GHz with a 0.8 V supply voltage. When the input signal frequencies are 3 and 17 GHz, the measured phase noises are -124.44 and -120.62 dBc/Hz at 10 MHz offset from the center frequency, respectively. The circuit occupies 412 μm × 338 μm and the total power consumption is only 3.84 mW.

引用

页码：1152 / 1156

页数：4

共 8 条

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