Combining half adder graph for equivalence checking of arithmetic circuits

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Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China [1 ]
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Zhejiang Daxue Xuebao (Gongxue Ban) | 2008年 / 8卷 / 1345-1349+1403期
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10.3785/j.issn.1008-973X.2008.08.012
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