A cell selection policy for an input-buffered packet switch

被引：0

作者：

Department of Computing Science, University of Batna, Algeria ^{[1
]}

不详 ^{[2
]}

机构：

[1] Department of Computing Science, University of Batna

[2] Department of Computer Science, University of Tizi Ouzou

来源：

Int J Comput Appl | 2006年 / 3卷 / 234-242期

关键词：

Benes network; Multistage Interconnection Network (MIN); Self routing; Switch; VHDL;

D O I：

10.1080/1206212X.2006.11441808

中图分类号：

学科分类号：

摘要：

The literature contains many theoretical solutions to the design of high-performance packet switches, related to buffering, selection, and routing functionalities. Different selection policies and scheduling algorithms providing 100% throughput, such as MSM, MWM, and the like, have been proposed. However, in practice many of them introduce a high complexity and are not feasible. In this paper, we suggest a simple cell selection policy implemented by hardware for an input-queuing architecture using a multistage interconnection network. The proposal is described and simulated using a VHDL language. Performances in terms of delay, throughput, and cell loss are evaluated.

引用

页码：234 / 242

页数：8

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