Pseudo three-dimensional topology optimization of chip heat sinks with various inlet-outlet arrangements

Topology optimization (TO) represents a significant advancement in heat sink design for microelectronic chips. Although two-dimensional (2D) TO is favored for its simplicity and lower computational cost, it lacks the accuracy of three-dimensional (3D) TO, omitting certain processes inherent to 3D models. This paper introduces a novel pseudo 3D TO model, which integrates a 2D thermo-fluid design layer with a 2D conductive base plate layer, specifically optimized for chip heat sink designs. Employing the variable density method, we establish a mathematical description of the pseudo 3D TO, incorporating governing equations for flow dynamics and temperature variations in both layers. A distinctive feature of this model is its consideration of thermal coupling in the dimension typically neglected by standard 2D TO models. We applied the pseudo 3D TO model to optimize heat sink structures across various inlet and outlet configurations, followed by rigorous analyses to compare flow and heat transfer performances. These comparisons offer critical insights into the advantages and trade-offs of each configuration. Ultimately, a 3D heat sink was reconstructed from the pseudo 3D optimization results, and a detailed numerical experiment was conducted to assess its thermal performance under realistic conditions, thereby validating the efficacy and reliability of the pseudo 3D TO model. The findings underscore the model's potential in achieving efficient and practical heat sink designs, balancing accuracy and computational efficiency.