Receiver design and realization of 40 Gbps very short reach optical transmission systems

被引:0
|
作者
Xu D. [1 ]
Hu Q. [1 ]
Miao P. [1 ]
机构
[1] Institute of RF- and OE-ICs, Southeast University
来源
Gaojishu Tongxin/Chinese High Technology Letters | 2010年 / 20卷 / 01期
关键词
12/16; conversion; Channel deskew; Converter IC; Frame synchronization; VSR5;
D O I
10.3772/j.issn.1002-0470.2010.01.014
中图分类号
学科分类号
摘要
The paper presents the receiver design and realization of a 40 Gbps very short reach (VSR) optical transmission system compatible for the OIF-VSR5 specification. The receiver consists of a converter IC and an optical receiver module, characterized by making full use of high speed transceivers in the field-programmable gate array (FPGA) to successfully realize 16 × 2.488 Gbps and 12 × 3.318Gbps signal transmission and reception. All of the functions of the converter IC such as clock data recovery, serial/parallel conversion, frame synchronization, channel deskew, 12/16 conversion and channel rearrangement are implemented in one FPGA chip. The frame synchronization logic based on the binary search algorithm can speed up the converter IC greatly. Testing results obtained from Signaltap II indicate that the circuit works well and correctly. Furthermore, this paper presents a point-to-point test of the VSR5 experiment system. By connecting transmitter and receiver through 7-meter 12-fiber multi-model ribbon, a SDH STM-256/OC768 40 Gbps point-to-point test was realized, and a low bit error rate of 10-12 was obtained.
引用
收藏
页码:82 / 88
页数:6
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