A PVT insensitive vernier-based time-to-digital converter with extended input range and high accuracy

A monolithic Vernier-based time-to-digital converter (TDC) with 37.5 ps time resolution and theoretically unlimited input range has been integrated in TSMC 0.35-mu m standard 2P4M CMOS technology. Since the proposed circuit utilizes a single-stage Vernier delay line (VDL) for both coarse and fine measurements, no other interpolation circuit is required. The operation frequencies of the single-stage Vernier delay line are stabilized against process, voltage and temperature (PVT) variations by dual phase-locked loops. The proposed TDC successfully eliminates the element mismatch, input range limitation, external bias adjustment and complicated calibration problems. The measured differential nonlinearity is +/- 0.2 LSB, and the measured integral nonlinearity is +/- 0.35 LSB. The power consumption is 150 mW at 100 k samples/s full conversion speed, and the chip size is as small as 0.222 mm(2). All the packaged chips were tested to be fully functional over -40 degrees C to 100 degrees C ambient temperature range and 3.0 V to 3.9 V supply voltage range with extremely low resolution variations.