A parallelized implementation of turbo decoding based on network on chip multi-core processor

被引：0
|
作者：
Zhang, Chaolong [1 ]
Hu, Zhekun [2 ]
Chen, Jie [1 ]
机构：
[1] Institute of Microelectronics, Chinese Academy of Sciences, Beijing 10029, China
[2] The 709th Research Institute of China Shipbuilding Industry Corporation, Wuhan 430009, China
来源：
Journal of Engineering Science and Technology Review | 2014年 / 7卷 / 01期
关键词：
D O I：
10.25103/jestr.071.09
中图分类号：
学科分类号：
摘要：
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页码：52 / 59
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