Design of cost-effective 2-level correlation indirect-branch predictor

被引：0

作者：

Yuan, Nan ^{[1
,2
]}

Fan, Dong-Rui ^{[1
]}

机构：

[1] Key Laboratory of Computer System and Architecture, Institute of Computing Technology, Chinese Acad. of Sci.

[2] Graduate University, Chinese Acad. of Sci.

来源：

Jisuanji Xuebao/Chinese Journal of Computers | 2008年 / 31卷 / 11期

关键词：

2-level correlation predictor; Indirect branch; Mispredict;

D O I：

10.3724/sp.j.1016.2008.01898

中图分类号：

学科分类号：

摘要：

Indirect branches occur frequently in Object-Oriented Language (OOL), and in Dynamically-Linked Libraries (DLL), two programming environments rapidly increasing in popularity. 2-level correlation indirect-branch predictor tracks branch behavior well but costs unaccepted hardware budget. Through analyzing principle of mis-prediction in 2-level correlation indirect-branch predictor, the authors propose several cost-effective methods like improving index function and storage compressing to reduce hardware cost of 2-level correlation indirect-branch predictor. With 133K-bit hardware storage budget, for a set of benchmarks comes from SPEC CPU2000, miss-prediction rate drops from 31% on 4-way set-associative BTB to 9.6% on proposed predictor, which is 2.3% larger than the optimal mis-prediction rate.

引用

页码：1898 / 1906

页数：8

共 17 条

[1]

Uh G.-R., Effectively exploiting indirect jumps, (1997)

[2]

Driesen K., Holzle U., Accurate indirect branch prediction, Proceedings of the International Symposium on Computer Architecture, pp. 167-178, (1998)

[3]

Sprangle E., Chappell R.S., Alsup M., Patt Y.N., The agree predictor: A mechanism for reducing negative branch history interference, Proceedings of the 24th International Symposium on Computer Architecture, pp. 284-291, (1997)

[4]

Lee C.-C., Chen I.-C.K., Mudge T.N., The bi-mode branch predictor, Proceedings of the 30th International Symposium on Microarchitecture, pp. 4-13, (1997)

[5]

Michaud P., Seznec A., Uhlig R., Trading conflict and capacity aliasing in conditional branch predictors, Proceedings of the 24th International Symposium on Computer Architecture, pp. 292-303, (1997)

[6]

Eden A.N., Mudge T., The YAGS branch prediction scheme, Proceedings of 31st International Symposium on Microarchitecture, pp. 69-77, (1998)

[7]

Yeh T., Patt Y., Two-level adaptive training branch prediction, Proceddings of the International Symposium on Microarchitecture, pp. 51-61, (1991)

[8]

Chang P., Hao E., Patt Y., Target prediction for indirect jumps, Proceedings of the International Symposium on Computer Architecture, pp. 274-283, (1997)

[9]

Driesen K., Holzle U., Limits of indirect prediction, (1997)

[10]

Driesen K., Holzle U., The cascaded predictor: Economic and adaptive branch target prediction, Proceedings of the 31st International Symposium on Microarchitecture, pp. 249-258, (1998)

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