Linearity improvement of cascode CMOS LNA using a diode connected NMOS transistor with a parallel RC circuit

被引：10

作者：

Chang C.-P. ^{[1
]}

Chien W.-C. ^{[1
]}

Su C.-C. ^{[1
]}

Wang Y.-H. ^{[1
]}

Chen J.-H. ^{[2
]}

机构：

[1] Department of Electrical Engineering, Institute of Microelectronics, National Cheng-Kung University, Tainan City 701, No. 1, University Road

[2] Department of Electrical Engineering, Tunghai University, Situn District Taichung City 407, No. 181, Sec. 3, Taichung Port Rd

来源：

Progress In Electromagnetics Research C | 2010年 / 17卷

关键词：

D O I：

10.2528/PIERC10082411

中图分类号：

学科分类号：

摘要：

A fully integrated 5.5 GHz high-linearity low noise amplifier (LNA) using post-linearization technique, implemented in a 0.18 μm RF CMOS technology, is demonstrated. The proposed technique adopts an additional folded diode with a parallel RC circuit as an intermodulation distortion (IMD) sinker. The proposed LNA not only achieves high linearity, but also minimizes the degradation of gain, noise figure (NF) and power consumption. The LNA achieves an input third-order intercept point (IIP3) of +8.33 dBm, a power gain of 10.02 dB, and a NF of 3.05 dB at 5.5 GHz biased at 6mA from a 1.8 V power supply.

引用

页码：29 / 38

页数：9

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