Design of reversible adder-subtractor and its mapping in optical computing domain

被引：0
|
作者：
Kotiyal, Saurabh [1 ]
Thapliyal, Himanshu [2 ]
Ranganathan, Nagarajan [1 ]
机构：
[1] Department of Computer Science and Engineering, University of South Florida, Tampa,FL, United States
[2] Department of Electrical and Computer Engineering, University of Kentucky, Lexington,KY, United States
来源：
Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) | 2014年 / 8911卷
关键词：
Adders - Computer circuits - Design - Optical data processing - Computation theory - Computing power - Low power electronics - Semiconductor optical amplifiers - Logic gates - Optical switches - Mach-Zehnder interferometers - Quantum computers;
D O I：
10.1007/978-3-662-45711-5_3
中图分类号：
学科分类号：
摘要：
引用
收藏
页码：37 / 55
相关论文
共 50 条
  • [1] Mapping of subtractor and adder-subtractor circuits on reversible quantum gates
    Thapliyal H.
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), 2016, 9570 : 10 - 34
  • [2] Controlled full adder-subtractor by vibrational computing
    Bomble, Laetitia
    Lauvergnat, David
    Remacle, Francoise
    Desouter-Lecomte, Michele
    PHYSICAL CHEMISTRY CHEMICAL PHYSICS, 2010, 12 (48) : 15628 - 15635
  • [3] A need of quantum computing: "Reversible logic synthesis of parallel binary adder-subtractor"
    Thapliyal, H
    Srinivas, M
    Arabnia, HR
    ESA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS AND APPLICATIONS, 2005, : 60 - 66
  • [4] LOGIC DESIGN EXAMPLE - FULL ADDER-SUBTRACTOR
    GABEL, RA
    IEEE TRANSACTIONS ON EDUCATION, 1975, 18 (03) : 171 - 173
  • [5] Design of Efficient Reversible BCD Adder-Subtractor Architecture and Its Optimization Using Carry Skip Logic
    Murugesan, Praveena
    Keppanagounder, Thanushkodi
    Natarajan, Vijeyakumar
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2016, 25 (07)
  • [6] LOGIC DESIGN EXAMPLE - FULL ADDER-SUBTRACTOR - REPLY
    KEIR, RA
    IEEE TRANSACTIONS ON EDUCATION, 1976, 19 (02) : 79 - 80
  • [7] Design of Optical Reversible Hybrid Adder-Subtractor Device Using Mach-Zehnder Interferometers for WDM Applications
    Chauhan C.
    Kaushik B.K.
    Kumar S.
    Journal of Optical Communications, 2022, 43 (04) : 539 - 548
  • [8] Modular Design of Ultra-Efficient Reversible Full Adder-Subtractor in QCA with Power Dissipation Analysis
    Firdous Ahmad
    Suhaib Ahmed
    Vipan Kakkar
    G. Mohiuddin Bhat
    Ali Newaz Bahar
    Shahjahan Wani
    International Journal of Theoretical Physics, 2018, 57 : 2863 - 2880
  • [9] Design and Modelling of Single Electron Transistor Based Reconfigurable Adder-Subtractor
    Rathnakannan, K.
    Ranjan, P. Vanaja
    JOURNAL OF NANOELECTRONICS AND OPTOELECTRONICS, 2008, 3 (03) : 289 - 296
  • [10] Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata
    Taherkhani, Elham
    Moaiyeri, Mohammad Hossein
    Angizi, Shaahin
    OPTIK, 2017, 142 : 557 - 563
12345